Fine-grained Critical Path Analysis and Optimization for Area-time Efficient Realization of Multiple Constant Multiplications

In this paper, a set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and antisymmetrical particular cases are also covered. In last two decades, many efficient algorithms and architectures have been introduced for the design of low complexity bit-parallel Multiple Constant Multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers alternative low complexity MCM operations at the cost of an increased delay. In this topic, we address the problem of optimizing the gate-level area in digit -serial MCM designs and introduce high level synthesis algorithms, design architectures, and a computer aided design tool. The proposed optimization algorithms for the digit-serial MCM architectures in the design of digit-serial MCM operations and finite impulse response filters yields better performance compared with multiple Constant multipliers using Common Sub-expression Elimination (CSE) algorithm with high efficiency.